diff -c irt-06\Makefile tricks\Makefile *** irt-06\Makefile Wed Oct 29 22:33:14 2014 --- tricks\Makefile Mon Nov 10 11:30:33 2014 *************** *** 12,18 **** MCU = cortex-m0 -mthumb # Target file name (without extension). ! TARGET = irt # select target model #MODEL = -DXPLR4330 --- 12,18 ---- MCU = cortex-m0 -mthumb # Target file name (without extension). ! TARGET = trick # select target model #MODEL = -DXPLR4330 diff -c irt-06\common.h tricks\common.h *** irt-06\common.h Sat Nov 01 01:31:06 2014 --- tricks\common.h Wed Nov 12 13:43:28 2014 *************** *** 59,64 **** --- 59,110 ---- /* =============================================================== */ /* + * misc signal cooking + * enable only one of these + */ + + /* + * trick1: make the signal inverted + * U1_TxD --> PIO0_2 + * ~PIO0_2 --> PIO0_3 (thru pattern match engine) + */ + #define MAKE_INVERT_of_U1_TxD 0 + + /* + * trick2: mask some signal by other + * U1_TxD --> PIO0_2 + * CTOUT_0 --> PIO0_17 + * ~PIO0_2 & PIO0_17 --> PIO0_3 (thru pattern match engine) + */ + #define MASK_CTOUT_by_TxD 0 + + /* + * trick3: make some signals OR'ed + * U1_TxD --> PIO0_2 + * CTOUT_0 --> PIO0_17 + * PIO0_2 | PIO0_17 --> PIO0_3 (thru pattern match engine) + */ + #define MAKE_CTOUT_OR_TxD 0 + + /* + * trick4: merge signals by illegal 'OR' operation + * U1_TxD --> PIO0_2 (output 2 functions to same pin) + * CTOUT_0 --> PIO0_2 (inhibited, by UM10601, Rev.1.6) + */ + #define MERGE_TxD_n_CTOUT 0 + + /* + * trick5: make single 2-input NAND logic + * PIO0_0 --> input-A + * PIO0_4 --> input-B + * output-Y --> PIO0_2 ... Y = not (A and B) + */ + #define MAKE_a_NAND 0 + + + /* =============================================================== */ + + /* * shared functions */ /* in common.c */ diff -c irt-06\main.c tricks\main.c *** irt-06\main.c Mon Nov 10 03:59:10 2014 --- tricks\main.c Wed Nov 12 13:43:34 2014 *************** *** 48,53 **** --- 48,57 ---- void def_HardFault_Handler(void) ATTR_INTR; void def_SVCall_Handler(void) ATTR_INTR; void def_PendSV_Handler(void) ATTR_INTR; + #if MAKE_a_NAND /* @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ */ + int nand_main(void); + void nand_configure_GPIO(u_long mainCLK); + #endif /* MAKE_a_NAND */ /* @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ */ /* * variables *************** *** 79,84 **** --- 83,92 ---- int sub_counter; int i, c; + #if MAKE_a_NAND /* @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ */ + nand_main(); /* never return */ + #endif /* MAKE_a_NAND */ /* @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ */ + /* * mask all interrupts by PRIMASK flag in the core */ *************** *** 98,103 **** --- 106,112 ---- * setup system clock for IRC 12MHz */ sysCLK = initial_sysCLK(/*use_PLL_or_set_divider=*/ 0); + // sysCLK = initial_sysCLK(/*use_PLL_or_set_divider=*/ -12); /* examine delay at 1MHz */ mainCLK = sysCLK * LPC_SYSCTL->SYSAHBCLKDIV; /* *************** *** 127,135 **** --- 136,250 ---- * initial peripherals */ uart1_c_init(2400, mainCLK); + #if MAKE_INVERT_of_U1_TxD + #else /* MAKE_INVERT_of_U1_TxD */ sctimer_c_init(sysCLK); + #endif /* MAKE_INVERT_of_U1_TxD */ init_SysTick(sysCLK); + #if MAKE_INVERT_of_U1_TxD + { + u_long n, tmp; + + /* + * assign PIO0_2 to IN7 + */ + LPC_SYSCTL->PINTSEL[7] = 2; + + /* + * setup PME + * (I can not kill slice 7, so use from here) + * (use octal values, be careful !) + */ + /* confirm it disabled */ + LPC_PININT->PMCTRL = 0x0; + /* select IN7 for SRC7, IN0 for others */ + LPC_PININT->PMSRC = (070000000 <<8); + /* 'invert' for CFG7, const '1' for others */ + LPC_PININT->PMCFG = (050000000 <<8) | 0x00; /* 'AND' all 8 slices */ + LPC_PININT->PMCTRL = 0x3; /* enable PME and RXEV(BMAT) */ + + /* + * assign GPIO_INT_BMAT to PIO0_3 by Switch matrix + */ + n = 8; + tmp = LPC_SWM->PINASSIGN[n]; + tmp &= ~(0xff <<24); + tmp |= ( 3 <<24); + LPC_SWM->PINASSIGN[n] = tmp; + } + #endif /* MAKE_INVERT_of_U1_TxD */ + + #if MASK_CTOUT_by_TxD + { + u_long n, tmp; + + /* + * assign PIO0_2 to IN7, PIO0_17 to IN6 + */ + LPC_SYSCTL->PINTSEL[7] = 2; + LPC_SYSCTL->PINTSEL[6] = 17; /* this pad does not have external pin */ + + /* + * setup PME + * (I can not kill slice 7, so use from here) + * (use octal values, be careful !) + */ + /* confirm it disabled */ + LPC_PININT->PMCTRL = 0x0; + /* select IN7 for SRC7, IN6 for SRC6, IN0 for others */ + LPC_PININT->PMSRC = (076000000 <<8); + /* 'invert' for CFG7, 'thru' for CFG6, const '1' for others */ + LPC_PININT->PMCFG = (054000000 <<8) | 0x00; /* 'AND' all 8 slices */ + /* enable PME and RXEV(BMAT) */ + LPC_PININT->PMCTRL = 0x3; + + /* + * assign GPIO_INT_BMAT to PIO0_3 by Switch matrix + */ + n = 8; + tmp = LPC_SWM->PINASSIGN[n]; + tmp &= ~(0xff <<24); + tmp |= ( 3 <<24); + LPC_SWM->PINASSIGN[n] = tmp; + } + #endif /* MASK_CTOUT_by_TxD */ + + #if MAKE_CTOUT_OR_TxD + { + u_long n, tmp; + + /* + * assign PIO0_2 to IN7, PIO0_17 to IN6 + */ + LPC_SYSCTL->PINTSEL[7] = 2; + LPC_SYSCTL->PINTSEL[6] = 17; /* this pad does not have external pin */ + + /* + * setup PME + * (I can not kill slice 7, so use from here) + * (use octal values, be careful !) + */ + /* confirm it disabled */ + LPC_PININT->PMCTRL = 0x0; + /* select IN7 for SRC7, IN6 for SRC6, IN0 for others */ + LPC_PININT->PMSRC = (076000000 <<8); + /* 'thru' for CFG7 & CFG6, const '0' for CFG3, '1' for others */ + LPC_PININT->PMCFG = (044006000 <<8) | 0x48; /* divide slices: 1+3+4 */ + /* enable PME and RXEV(BMAT) */ + LPC_PININT->PMCTRL = 0x3; + + /* + * assign GPIO_INT_BMAT to PIO0_3 by Switch matrix + */ + n = 8; + tmp = LPC_SWM->PINASSIGN[n]; + tmp &= ~(0xff <<24); + tmp |= ( 3 <<24); + LPC_SWM->PINASSIGN[n] = tmp; + } + #endif /* MAKE_CTOUT_OR_TxD */ + /* * start my job */ *************** *** 497,499 **** --- 612,855 ---- } /* =============================================================== */ + + + #if MAKE_a_NAND + /* @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ */ + /* @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ */ + + /* + * main.c - main for "single 2-input NAND gate" + * by uratan! 2014.11.11 + */ + /* + * I/O pin usage + * pin#8: PIO0_0 (input) - input A + * pin#2: PIO0_4 (input) - input B + * pin#4: PIO0_2 (output) - Y = not (A and B) + */ + #define GPI_A (1<<0) + #define GPI_B (1<<4) + #define GPO_Y (1<<2) + + /* + * options for output + */ + #define KEEP_PULL_UP_at_OUTPUT 1 + + /* + * options for inputs + */ + #define KEEP_PULL_UP_at_INPUTs 1 + #define ADD_HYSTERESIS 0 + #define USE_GLITCH_FILTER 0 + + /* + * config for system condition + */ + #define DISABLE_sysCLK 0 + /* + * sysCLK is necessary ! + * RXEV/BMAT may be synced with sysCLK at final stage... + */ + + /* + * functions + */ + ////////int nand_main(void); + ////////void nand_configure_GPIO(u_long mainCLK); + + + /* =============================================================== */ + + /* + * + */ + int nand_main(void) + { + u_long sysCLK; + u_long mainCLK; + u_long n, tmp; + + /* + * mask all interrupts by PRIMASK flag in the core + */ + __disable_irq(); + + /* + * configure I/O pins + */ + configure_fixed_pins(); + + /* + * setup system clock for IRC 12MHz + */ + sysCLK = initial_sysCLK(/*use_PLL_or_set_divider=*/ 0); + // sysCLK = initial_sysCLK(/*use_PLL_or_set_divider=*/ -12); /* examine delay at 1MHz */ + mainCLK = sysCLK * LPC_SYSCTL->SYSAHBCLKDIV; + + /* + * configure GPIO after clock fixed + */ + nand_configure_GPIO(mainCLK); + + /* + * setup Pattern Match Engine + */ + /* + * assign PIO0_0 to IN7, PIO0_4 to IN6 + */ + LPC_SYSCTL->PINTSEL[7] = 0; + LPC_SYSCTL->PINTSEL[6] = 4; + + /* + * setup PME + * (I can not kill slice 7, so use from here) + * (use octal values, be careful !) + */ + /* confirm it disabled */ + LPC_PININT->PMCTRL = 0x0; + /* select IN7 for SRC7, IN6 for SRC6, IN0 for others */ + LPC_PININT->PMSRC = (076000000 <<8); + /* 'invert' for CFG7 & CFG6, '0' for others */ + LPC_PININT->PMCFG = (055666666 <<8) | 0x60; /* divide slices: 1+1+6 */ + /* enable PME and RXEV(BMAT) */ + LPC_PININT->PMCTRL = 0x3; + + /* + * assign GPIO_INT_BMAT to PIO0_2 by Switch matrix + */ + n = 8; + tmp = LPC_SWM->PINASSIGN[n]; + tmp &= ~(0xff <<24); + tmp |= ( 2 <<24); + LPC_SWM->PINASSIGN[n] = tmp; + + #if DISABLE_sysCLK + /* + * test without clock + */ + LPC_SYSCTL->SYSAHBCLKDIV = 0; + //LPC_SYSCTL->SYSAHBCLKDIV = 250; + #endif /* DISABLE_sysCLK */ + + /* + * I have no jobs + */ + // __enable_irq(); + + while(1) { + ; + } + + /* never return */ + } + + /* =============================================================== */ + + /* + * + */ + void nand_configure_GPIO(u_long mainCLK) + { + #if USE_GLITCH_FILTER + u_long div; + #endif /* USE_GLITCH_FILTER */ + u_long n, tmp; + + /* + * prevent the the open-drain pins from internally floating + * (PIO0_10 and PIO0_11, section 6.3, UM10601) + */ + ////////#define INTERNAL_OPEN_DRAIN_PINS ((1<<10) | (1<<11)) + LPC_GPIO_PORT->CLR[0] = INTERNAL_OPEN_DRAIN_PINS; /* both Low */ + LPC_GPIO_PORT->DIR[0] |= INTERNAL_OPEN_DRAIN_PINS; /* start to drive */ + + /* + * setup GPIO + */ + LPC_GPIO_PORT->DIR[0] &= ~(GPI_A | GPI_B); /* confirm input */ + LPC_GPIO_PORT->DIR[0] &= ~GPO_Y; /* confirm not to drive */ + /* + * start to drive when BMAT is assigned by SWM + */ + + #if USE_GLITCH_FILTER + /* + * use glitch filter for the input + */ + /* + * setup filter clock: maybe 12MHz / 240 = 50kHz + */ + div = mainCLK / 50 * 1000; /* 50kHz */ + if(div > 255) { + div = 255; + } + LPC_SYSCTL->IOCONCLKDIV[6 - 0] = div; /* select CLK0 */ + #endif /* USE_GLITCH_FILTER */ + + /* + * setup I/O configuration + */ + LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << SYSCTL_CLOCK_IOCON); + + /* + * configure output + */ + n = IOCON_PIO2; + tmp = LPC_IOCON->PIO0[n]; + #if KEEP_PULL_UP_at_OUTPUT + #else /* KEEP_PULL_UP_at_OUTPUT */ + tmp &= ~PIN_MODE_MASK; + tmp |= (PIN_MODE_INACTIVE <PIO0[n] = tmp; + + /* + * configure input A + */ + n = IOCON_PIO0; + tmp = LPC_IOCON->PIO0[n]; + #if KEEP_PULL_UP_at_INPUTs + #else /* KEEP_PULL_UP_at_INPUTs */ + tmp &= ~PIN_MODE_MASK; + tmp |= (PIN_MODE_INACTIVE <PIO0[n] = tmp; + + /* + * configure input B + */ + n = IOCON_PIO4; + tmp = LPC_IOCON->PIO0[n]; + #if KEEP_PULL_UP_at_INPUTs + #else /* KEEP_PULL_UP_at_INPUTs */ + tmp &= ~PIN_MODE_MASK; + tmp |= (PIN_MODE_INACTIVE <PIO0[n] = tmp; + + LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << SYSCTL_CLOCK_IOCON); + } + + /* @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ */ + /* @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ */ + #endif /* MAKE_a_NAND */ diff -c irt-06\sctimer.c tricks\sctimer.c *** irt-06\sctimer.c Fri Oct 31 17:51:05 2014 --- tricks\sctimer.c Mon Nov 10 15:48:45 2014 *************** *** 34,40 **** --- 34,46 ---- n = 6; tmp = LPC_SWM->PINASSIGN[n]; tmp &= ~(0xff <<24); + #if MASK_CTOUT_by_TxD || MAKE_CTOUT_OR_TxD + tmp |= ( 17 <<24); /* PIO0_17 (internal only) */ + #elif MERGE_TxD_n_CTOUT + tmp |= ( 2 <<24); /* PIO0_2 */ + #else /* MASK_CTOUT_by_TxD || MAKE_CTOUT_OR_TxD || MERGE_TxD_n_CTOUT */ tmp |= ( 3 <<24); + #endif /* MASK_CTOUT_by_TxD || MAKE_CTOUT_OR_TxD || MERGE_TxD_n_CTOUT */ LPC_SWM->PINASSIGN[n] = tmp; /* *************** *** 127,132 **** --- 133,140 ---- LPC_SCT->OUT[3].SET = 0; /* do not use OUT3 */ LPC_SCT->OUT[3].CLR = 0; /* do not use OUT3 */ + #if MERGE_TxD_n_CTOUT + #else /* MERGE_TxD_n_CTOUT */ /* * finally, disable pull-up-R on PIO0_3 */ *************** *** 139,144 **** --- 147,153 ---- LPC_IOCON->PIO0[n] = tmp; LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << SYSCTL_CLOCK_IOCON); + #endif /* MERGE_TxD_n_CTOUT */ // /* // * start the counter