/* * project "vgaC" * by uratan! 2012.4.23 */ /* * index * SYSTEM BLOCK DIAGRAM * MEMORY MAP * REGISTERS * BITWISE REGISTERS * CAPTURE TIMING * BUS SEQUNCE * DATA FORMAT * VGA STANDARD REFRESH RATES * FRAME RATE TRIAL CALCULATION * THINK ABOUT CLOCK AGAIN * Spartan3 DCM PLL RESTRICTION * FreeBSD vidcontrol * SCSI COMMANDs */ /* * SYSTEM BLOCK DIAGRAM * * +----+ USB1.1 * | PC |-------+ MassStorageClass PhotoMosRelay-+--> Power-SW * +----+ | (BBB, SCSI) | (option) +--> Reset-SW * +-----------------------------------------+ * | usb NXP LPC2148 gpio | core: 36MHz * | aout pwm gpio eint | peripheral: 36MHz * +-----------------------------------------+ * | |18MHz | ^ * | | | res,cs,rw | EINT * | | v data,strobe | * | | +----------------------------------------+ * | | | +---------------+ +-----------------+ | * | V | | bus sequencer | | intr controller | | * | +----+ +---------------+ +-----------------+ | * osc | | +-----+ | ^ | * 24MHz --|--->| | DCM |-> 126MHz | +---------------+ | | * (option) | | +-----+ +----| dual port RAM | | | * | | | +------8kB/24kB-+ | | * | | Xilinx | | | | * | | XC3S50/200 | +-------------+ | * | | | | | | * | | +-----------+--+---------| capture | | * | | | | | control | | * | | +------+ +--------------+ | unit | | * | | | bias | | measure unit | | | | * | | +------+ +--------------+ +-------------+ | * | +---------------------------------------------+ * | |(option) ^ ^ * +----o o-+ | VS,HS | R,G,B (1+1+1bit) * | +--------------------+ * +------------->| analog circuit | * BIAS +--------------------+ * ^ (720x400@70Hz) * | VGA (640x480@60Hz) * +-------------+ (1024x768@60Hz) * (EDID ???) | target PC | * (USB2.0 High-Speed ???) +-------------+ */ /* * MEMORY MAP * * addr * from to description * -------------------------------------------------------------- * 0x0000--0x001f registers * 0x0020--0x7fff images of registers * 0x8000--0x9fff capture memory (8k bytes) * 0xa000--0xffff images of memories * (0x8000--0xdfff capture memory (24k bytes)) * (0xe000--0xffff images of memories) * -------------------------------------------------------------- */ /* * REGISTERS * * addr rw width name description [unit] * -------------------------------------------------------------- * 0x00 w 16 ADDR_H address pointer * 0x01 w ADDR_L * 0x02 r 8 VERSION fpga version * 0x03 rw 8 BIAS bias outpout for analog (option) * 0x04 rw bw I_SENSE interrupt sense * 0x05 rw bw I_ENABLE interrupt enable * 0x06 r bw VGA_STAT raw vga signal * 0x07 r bw SYNC_STAT vsync/hsync status * -------------------------------------------------------------- * 0x08 r 8 V_PERIOD_H period of vsync [0.1msec] * 0x09 r V_PERIOD_L `ifdef CK126MHz * 0x0a r 9 H_PERIOD_H period of hsync [0.103usec] * 0x0b r H_PERIOD_L `else /* CK126MHz */ * 0x0a r 9 H_PERIOD_H period of hsync [0.1usec] * 0x0b r H_PERIOD_L `endif /* CK126MHz */ * 0x0c r 11 CUR_LINE_H current line number * 0x0d r CUR_LINE_L * 0x0e r 11 MAX_LINE_H max line number * 0x0f r MAX_LINE_L * -------------------------------------------------------------- `ifdef CK126MHz * 0x10 rw 13 C_DELAY_H capture delay from hsync [7.9nsec] * 0x11 rw C_DELAY_L `else /* CK126MHz */ * 0x10 rw 12 C_DELAY_H capture delay from hsync [10nsec] * 0x11 rw C_DELAY_L `endif /* CK126MHz */ * 0x12 rw 11 C_N_DOTS_H number of capture pixels * 0x13 rw C_N_DOTS_L * 0x14 rw 11 C_N_LINES_H number of capture lines * 0x15 rw C_N_LINES_L * 0x16 rw 11 C_TARGET_H capture target line number * 0x17 rw C_TARGET_L * -------------------------------------------------------------- * 0x18 rw bw C_OPTIONS capture options * 0x19 rw bw C_EXEC execute capture * 0x1a rw * 0x1b rw bw TEST test mode, monitor select * 0x1c r 16 C_BUFSIZE_H capture buffer size [byte] * 0x1d r C_BUFSIZE_L * 0x1e rw 16 (ABF_SIZ_H) buffer size of ARM firmware [byte] * 0x1f rw (ABF_SIZ_L) (ARM write for memorandom) * -------------------------------------------------------------- * (you may write (n-1) if you want ...) */ /* * BITWISE REGISTERS * * I_SENSE +------+------+------+------++------+------+------+------+ * | bit7 | bit6 | bit5 | bit4 || bit3 | bit2 | bit1 | bit0 | * +------+------+------+------++------+------+------+------+ * | REQ | | | || | | | | * +------+------+------+------++------+------+------+------+ * REQ: 0: no request * 1: capture done (write 0 to clear) * * I_ENABLE +------+------+------+------++------+------+------+------+ * | bit7 | bit6 | bit5 | bit4 || bit3 | bit2 | bit1 | bit0 | * +------+------+------+------++------+------+------+------+ * | ENB | POL | | || | | | | * +------+------+------+------++------+------+------+------+ * ENB: 0: mask external INTR wire * 1: enable external INTR wire * POL: 0: INTR wire is low active * 1: INTR wire is high active * * VGA_STAT +------+------+------+------++------+------+------+------+ * | bit7 | bit6 | bit5 | bit4 || bit3 | bit2 | bit1 | bit0 | * +------+------+------+------++------+------+------+------+ * | CK126| | VSYN | HSYN || | G | R | B | * +------+------+------+------++------+------+------+------+ * VSYN: raw vsync signal * HSYN: raw hsync signal * G: raw green signal * R: raw red signal * B: raw blue signal `ifdef CK126MHz * CK126: 0: 100MHz * 1: 126MHz `endif /* CK126MHz */ * * SYNC_STAT +------+------+------+------++------+------+------+------+ * | bit7 | bit6 | bit5 | bit4 || bit3 | bit2 | bit1 | bit0 | * +------+------+------+------++------+------+------+------+ * | VOVF | VTGL | | VPOL || HOVF | HTGL | | HPOL | * +------+------+------+------++------+------+------+------+ * VOVF: 0: VSYNC may be correct * 1: no VSYNC has come * VTGL: x: toggle when VSYNC has come * VPOL: 0: VSYNC input has positive polarity * 1: VSYNC input has negative polarity * HOVF: 0: HSYNC may be correct * 1: no HSYNC has come * HTGL: x: toggle when HSYNC has come * HPOL: 0: HSYNC input has positive polarity * 1: HSYNC input has negative polarity * * C_OPTIONS +------+------+------+------++------+------+------+------+ * | bit7 | bit6 | bit5 | bit4 || bit3 | bit2 | bit1 | bit0 | * +------+------+------+------++------+------+------+------+ * | DBL | SIDE | MOD || | PACK | * +------+------+------+------++------+------+------+------+ * //DBL: 0: single buffer mode (sideA + sideB) * // 1: double buffer mode, SIDE is valid * //SIDE: 0: store into memory sideA * // 1: store into memory sideB `ifdef CK126MHz * MOD: 0: sample rate 63MHz (126MHz/2) * 1: sample rate 42MHz (126MHz/3) * 2: sample rate 32MHz (126MHz/4) * 3: sample rate 25MHz (126MHz/5) `else /* CK126MHz */ * MOD: 0: sample rate 100MHz (100MHz/1) * 1: sample rate 50MHz (100MHz/2) * 2: sample rate 33MHz (100MHz/3) * 3: sample rate 25MHz (100MHz/4) `endif /* CK126MHz */ * PACK: 0: store 1 pixel / byte (8'b1000_0grb) * 1: pack 2 pixels / byte (8'b1grb_0grb) * 2: pack 8 pixels / byte (g only) * 3: pack 8 pixels / byte (r only) * 4: pack 8 pixels / byte (b only) * 5: pack 8 pixels / byte (g OR r OR b) * 6: pack 8 pixels / byte (g AND r AND b) * 7: pack 8 pixels / byte (g XOR r XOR b) * * C_EXEC +------+------+------+------++------+------+------+------+ * | bit7 | bit6 | bit5 | bit4 || bit3 | bit2 | bit1 | bit0 | * +------+------+------+------++------+------+------+------+ * | EXEC | | | || | | | | * +------+------+------+------++------+------+------+------+ * EXEC: 1: start capture * 0: finished / write 0 to terminate capture * * TEST +------+------+------+------++------+------+------+------+ * | bit7 | bit6 | bit5 | bit4 || bit3 | bit2 | bit1 | bit0 | * +------+------+------+------++------+------+------+------+ * | WP | DFIL | | || | MON_LED_SEL | * +------+------+------+------++------+------+------+------+ * WP: 0: capture unit can write to buffer * 1: CPU can write buffer from bus * DFIL 0: use VSYNC/HSYNC noise filter * 1: disable it * MON_LED_SEL: ... see top.v near 'sel_mon_led' */ /* * CAPTURE TIMING * * 31.5kHz(31.7usec) / line * |<---------------------------------------- ------->| * HSYNC --+ +----------------------------------------- -----+ +-- * | | | | * +--+ |<->| dotclock:25MHz +--+ * | +---+ +---+ +---+ +-- * V | | | | | | | * R,G,B --------------------+ +---+ +---+ +---+ ----------- * | C_DELAY ||||||||| ... sample rate: 100MHz * |---------------> VVVVVVVVV * capture [10ns] ********* ... C_N_DOTS * * | +---+ +---+ +---+ +-- * V | | | | | | | * R,G,B --------------------+ +---+ +---+ +---+ ----------- * | C_DELAY | | | | | | | | | | ... sample rate: 50MHz * |---------------> V V V V V V V V V V * capture [10ns] * * * * * * * * * * ... C_N_DOTS * */ /* * BUS SEQUENCE * * (signals below are once synced with CLK) * * ***** WRITE BUS CYCLE *************************************************** * (100MHz) * CLK | | | | | | | | | | | | | | | | | | | | | * V V V V V V V V V V V V V V V V V V V V V * * ---+ +-- * RxW | | * +--*-----------------------------------------------------+ * | * ------+ +----- * xCS | | * +--------------------------------------------------+ * | * ---------+ +--*--+ *--*-----+ +--*-------- * xSTRB | | | | | | | | | | * | +==*==*==* | +==*==*==*==* | +==*==* | * V | | | V | | | | V | | V * ______ _____________ ________________ _____________ _______ * addr x >< 0 >< 1 >< HL >< HL+1 * (internal)~~~ ~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~ ~~~~~~~ * | | | | | | | | | * _________ ____________ ______ * DATA ---------< addr-H >----< addr-L >-------< Data >---------- * ~~~~~~~~~ ~~~~~~~~~~~~ ~~~~~~ * fetch | | | | | | | | | * V V V V V V V V V * [[ Internal Addr Registers ]] [[ Target ]] * * ***** READ BUS CYCLE **************************************************** * (100MHz) * CLK | | | | | | | | | | | | | | | | | | | | | * V V V V V V V V V V V V V V V V V V V V V * * ---+--------------------------------------------------------+-- * RxW (keep high) * * * ------+ +----- * xCS | | * +--------------------------------------------------+ * | | * ---------+ +--*--+ +--*-----+ +--*-------- * xSTRB | | | | | | | | | | | * | +--------+ | +-----------+ | +-----+ | | * | V V V | * _____________________ ________________ _____________ _______ * addr m >< m+1 >< m+2 >< m+3 * (internal)~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~ ~~~~~~~ * | | | | | * V______________V ________________V _____________V V * DATA --z---< A >< B >< C ><>---z-- * ~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~ */ /* * DATA FORMAT * * examples when PACK==0 * * -- 1 pixel captured ------------------------------------------ * 0x8000 8'b1111_1111 - line header * 0x8001 8'b1000_0GRB - captured pixel * * -- 2 pixel captured ------------------------------------------ * 0x8000 8'b1111_1111 - line header * 0x8001 8'b1000_0GRB - captured pixel * 0x8002 8'b1000_0GRB - captured pixel * * -- 3 pixel captured ------------------------------------------ * 0x8000 8'b1111_1111 - line header * 0x8001 8'b1000_0GRB - captured pixel * 0x8002 8'b1000_0GRB - captured pixel * 0x8003 8'b1000_0GRB - captured pixel * * -- 16 pixel captured ----------------------------------------- * 0x8000 8'b1111_1111 - line header * 0x8001 8'b1000_0GRB - captured pixel * 0x8002 8'b1000_0GRB - captured pixel * 0x8003 8'b1000_0GRB - captured pixel * ... * 0x8010 8'b1000_0GRB - captured pixels * -------------------------------------------------------------- * * examples when PACK==1 * * -- 1 pixel captured ------------------------------------------ * 0x8000 8'b1111_1111 - line header * 0x8001 8'b1GRB_1111 - captured pixel * * -- 2 pixel captured ------------------------------------------ * 0x8000 8'b1111_1111 - line header * 0x8001 8'b1GRB_0GRB - captured pixels * * -- 3 pixel captured ------------------------------------------ * 0x8000 8'b1111_1111 - line header * 0x8001 8'b1GRB_0GRB - captured pixels * 0x8002 8'b1GRB_1111 - captured pixel * * -- 16 pixel captured ----------------------------------------- * 0x8000 8'b1111_1111 - line header * 0x8001 8'b1GRB_0GRB - captured pixels * 0x8002 8'b1GRB_0GRB - captured pixels * ... * 0x8008 8'b1GRB_0GRB - captured pixels * -------------------------------------------------------------- * * examples when PACK==2--7 * * -- 1 pixel captured ------------------------------------------ * 0x8000 8'b1111_1111 - line header * 0x8001 8'bP000_0000 - captured pixel * * -- 2 pixel captured ------------------------------------------ * 0x8000 8'b1111_1111 - line header * 0x8001 8'bPP00_0000 - captured pixels * * -- 3 pixel captured ------------------------------------------ * 0x8000 8'b1111_1111 - line header * 0x8001 8'bPPP0_0000 - captured pixels * * -- 16 pixel captured ----------------------------------------- * 0x8000 8'b1111_1111 - line header * 0x8001 8'bPPPP_PPPP - captured pixels * 0x8002 8'bPPPP_PPPP - captured pixels * -------------------------------------------------------------- */ /* * VGA STANDARD REFRESH RATES * * HSYNC VSYNC dotclock * ----------+---------+------+----------- * 640x480 | 31.5kHz | 60Hz | 25.175MHz <== (1) * | 37.9kHz | 72Hz | 31.5MHz * | 37.5kHz | 75Hz | 31.5MHz * ----------+---------+------+----------- * 720x400 | 31.5kHz | 70Hz | 28.3MHz <== (2) * ----------+---------+------+----------- * 800x600 | 35.1kHz | 56Hz | 36.0MHz * | 37.9kHz | 60Hz | 40.0MHz * | 48.1kHz | 72Hz | 50.0MHz * | 46.9kHz | 75Hz | 49.5MHz * ----------+---------+------+----------- * 1024x768 | 48.4kHz | 60Hz | 65.0MHz <== (3) * | 56.5kHz | 70Hz | 75.0MHz * | 60.0kHz | 75Hz | 78.75MHz * ----------+---------+------+----------- * 1280x1024| 64.0kHz | 60Hz | 108.0MHz <== (4) * | 80.0kHz | 75Hz | 135.0MHz * ----------+---------+------+----------- */ /* * FRAME RATE TRIAL CALCULATION * * 31.5kHz / 640Pixel ==> 20.2MB/s (single) * ==> 10.1MB/s (packed by 2) * ==> 2.5Mb/s (packed by 8) * * 640x480 / 60Hz ==> 18.4MB/s (single) * ==> 9.2MB/s (packed by 2) * ==> 2.3MB/s (packed by 8) * * USB1.1 / HID 64*1000 ==> 64kB/s * / BBB ==> 1MB/s * * 640x480 ==> 307kB/frame (single) * ==> 154kB/frame (packed by 2) * ==> 38kB/frame (packed by 8) * * USB1.1 / HID ==> 4.8 [sec/frame] (single) * ==> 2.4 [sec/frame] (packed by 2) * ==> 1.7 [frame/sec] (packed by 8) * * USB1.1 / BBB ==> 3.3 [frame/sec] (single) * ==> 6.5 [frame/sec] (packed by 2) * ==> 26.0 [frame/sec] (packed by 8) * */ /* * THINK ABOUT CLOCK AGAIN * * taget: * * 640x480 | 31.5kHz | 60Hz | 25.175MHz <== (1) near 25MHz * | 37.9kHz | 72Hz | 31.5MHz near 31.5MHz * 720x400 | 31.5kHz | 70Hz | 28.3MHz <== (2) near 28MHz * 1024x768 | 48.4kHz | 60Hz | 65.0MHz <== (3) near 65MHz * (1280x1024| 64.0kHz | 60Hz | 108.0MHz <== (4) don't care) * * -------+----------------------------------------------------------------- * base | * clock | 1/2--> 1/3--> 1/4--> 1/5--> 1/6--> 1/7--> 1/8 * -------+----------------------------------------------------------------- * 100MHz | 50.0 +33.3 +25.0 * 110MHz | 55.0 36.7 +27.5 * 120MHz | +60.0 40.0 +30.0 * 130MHz | +65.0 43.3 +32.5 +26.0 <===! * 140MHz | +70.0 46.7 35.0 +28.0 * 150MHz | 75.0 50.0 37.5 +30.0 +25.0 * 160MHz | 80.0 53.3 40.0 +32.0 +26.7 * 170MHz | 85.0 56.7 42.5 34.0 +28.3 * 180MHz | 90.0 +60.0 45.0 36.0 +30.0 +25.7 * 190MHz | 95.0 +63.3 47.5 38.0 +31.7 +27.1 * 200MHz |100.0 +66.7 50.0 40.0 +33.3 +28.6 +25.0 * -------+----------------------------------------------------------------- * * 25.175MHz x 5 => 125.875MHz (just!) * 31.500MHz x 4 => 126.000MHz (just!) * 126.000MHz / 2 => 63.000MHz (a little low) * * (higher clock -> over sample -> expand X width, larger data) * (lower clock -> under sample -> shorten X width, smaller data) * ==> a little low clock is better * (in fact, I had sample width 720 as 640 with 25MHz) * ====> I shall choice 126MHz */ /* * Spartan3 DCM PLL RESTRICTION * * fout = fin * M / N (M: 2--32, N: 1--32) * * 24MHz * 11/2 = 132MHz * 24MHz * xx/x = 130MHz ... unselectable * 24MHz * 16/3 = 128MHz ... 128/ 64/ 42.7/ 32/ 25.6 * 24MHz * 21/4 = 126MHz ... 126/ 63/ 42/ 31.5/ 25.2 <=== THIS! * 24MHz * 25/6 = 100MHz ... 100/ 50/ 33/ 25 * 24MHz * 11/4 = 66MHz * 24MHz * 8/3 = 64MHz * 24MHz * 21/8 = 63MHz * 24MHz * 31/12= 62MHz * * 48MHz * 11/4 = 132MHz * 48MHz * xx/x = 130MHz ... unselectable * 48MHz * 8/3 = 128MHz * 48MHz * 21/8 = 126MHz * 48MHz * 25/12= 100MHz * 48MHz * 11/8 = 66MHz * 48MHz * 4/3 = 64MHz * 48MHz * 21/16= 63MHz * 48MHz * 31/24= 62MHz * * 18MHz * 22/3 = 132MHz * 18MHz * x/x = 130MHz ... unselectable * 18MHz * x/x = 128MHz ... unselectable * 18MHz * 7/1 = 126MHz * 18MHz * x/x = 100MHz ... unselectable * 18MHz * 11/3 = 66MHz * 18MHz * x/x = 65MHz ... unselectable * 18MHz * 32/9 = 64MHz * 18MHz * 7/2 = 63MHz * 18MHz * 31/9 = 62MHz */ /* * FreeBSD vidcontrol * * +------------------------- * |% vidcontrol 80x30 ---> 640x480@60Hz * |% vidcontrol VGA_80x30 ---> (same above) * |% vidcontrol 80x25 ---> 720x400@70Hz * |% vidcontrol VGA_80x25 ---> (same above) * |% vidcontrol show ---> show attribute examples * +------------------------- */ /* * SCSI COMMANDs * * STANDARD COMMANDs * * CDB_TEST_UNIT_READY * +------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | * +------+------+------+------+------+------+ * | 0x00 | | | | | | * +------+------+------+------+------+------+ * * CDB_INQUIRY * +------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | * +------+------+------+------+------+------+ * | 0x12 | | | | ALen | | * +------+------+------+------+------+------+ * ALen: ALLOCATION LENGTH * * CDB_REQUEST_SENSE * +------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | * +------+------+------+------+------+------+ * | 0x03 | | | | ALen | | * +------+------+------+------+------+------+ * ALen: ALLOCATION LENGTH * * VENDOR UNIQUEs * * CDB_VGAC_GET_INFO - get system / current VGA status, etc. * +------+------+------+------+------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | * +------+------+------+------+------+------+------+------+------+------+ * | 0xC0 | | | | | | | | ALen | | * +------+------+------+------+------+------+------+------+------+------+ * ALen: ALLOCATION LENGTH * * CDB_VGAC_SET_BIAS - set BIAS of analog circuit * +------+------+------+------+------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | * +------+------+------+------+------+------+------+------+------+------+ * | 0xC1 | | BIAS | | | | | | | | * +------+------+------+------+------+------+------+------+------+------+ * BIAS: value for BIAS (default is 0x00) * * * CDB_VGAC_SET_OPTION - set capture option * +------+------+------+------+------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | * +------+------+------+------+------+------+------+------+------+------+ * | 0xC2 | | OPT | | | | | | | | * +------+------+------+------+------+------+------+------+------+------+ * OPT: value for C_OPTIONS (default is 0x20) * * CDB_VGAC_CAPTURE - execute capture action * +------+------+------+------+------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | * +------+------+------+------+------+------+------+------+------+------+ * | 0xC3 | DBUF | C_DELAY | C_N_DOTS | C_N_LINES | C_TARGET_L | * +------+------+------+------+------+------+------+------+------+------+ * DBUF: 0x00: normal (return data after capture) * 0x01: double buffered (return previous data + start new) * * see top of returned data * 0xFF: shall have correct capture data * 0xEE: buffer overflow, data lost * 0xAA: capture failed, shall have vgac info's * 0x00: buffer NULL (when first use of DBUF mode) * * CDB_VGAC_READ_BUFF - simply return LPC's buffer (for test) * +------+------+------+------+------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | * +------+------+------+------+------+------+------+------+------+------+ * | 0xC4 | | offset | length | | | | | * +------+------+------+------+------+------+------+------+------+------+ * offset: ignored * * CDB_VGAC_WRITE_BUFF - simply write to LPC's buffer (for test) * +------+------+------+------+------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | * +------+------+------+------+------+------+------+------+------+------+ * | 0xC5 | | offset | length | | | | | * +------+------+------+------+------+------+------+------+------+------+ * offset: ignored * * CDB_VGAC_GET_PMR_STATE - get state of (optional) PMRs * +------+------+------+------+------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | * +------+------+------+------+------+------+------+------+------+------+ * | 0xC6 | | | | | | | | ALen | | * +------+------+------+------+------+------+------+------+------+------+ * ALen: ALLOCATION LENGTH * * CDB_VGAC_PMR_CONTROL - control (optional) PMRs * +------+------+------+------+------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | * +------+------+------+------+------+------+------+------+------+------+ * | 0xC7 | | PMR# |on/off| | | | | | | * +------+------+------+------+------+------+------+------+------+------+ * 1:on 0:off * * CDB_FUPDATE_ERASE - erase sub area of flash * +------+------+------+------+------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | * +------+------+------+------+------+------+------+------+------+------+ * | 0xD0 | | | | | | | | | | * +------+------+------+------+------+------+------+------+------+------+ * * CDB_FUPDATE_WRITE - write to sub area of flash * +------+------+------+------+------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | * +------+------+------+------+------+------+------+------+------+------+ * | 0xD1 | | | | length | | | | | * +------+------+------+------+------+------+------+------+------+------+ * * CDB_FUPDATE_REBOOT - copy codes on sub area to master, then reboot * +------+------+------+------+------+------+------+------+------+------+ * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | * +------+------+------+------+------+------+------+------+------+------+ * | 0xD2 | | | | | | | | | | * +------+------+------+------+------+------+------+------+------+------+ * */