*** ..\spifi.c	Thu Oct 25 09:39:25 2012
--- spifi.c	Thu Nov 22 10:36:09 2012
***************
*** 112,118 ****
  #define CLOCK   12	/* SCK [MHz]
  					 *   the doc says that this is almost meaningless now
  					 */
! #define CS_HIGH  3	/* tcs [SCK]
  					 *   command interval, determined by chip spec
  					 *   S25FL032P:
  					 *     tcs(CS# High Time): 10ns (Read)
--- 112,118 ----
  #define CLOCK   12	/* SCK [MHz]
  					 *   the doc says that this is almost meaningless now
  					 */
! #define CS_HIGH  1	/* tcs [SCK]
  					 *   command interval, determined by chip spec
  					 *   S25FL032P:
  					 *     tcs(CS# High Time): 10ns (Read)
*** ..\..\minimon-011\test-spifi\main.c	Sun Nov 11 07:20:56 2012
--- main.c	Thu Nov 22 11:42:31 2012
***************
*** 10,16 ****
  /*
   * reset myself if SPIFI is configured unproperly
   */
! #define ENABLE_SPIFI_RETRY  0
  
  /*
   *
--- 10,16 ----
  /*
   * reset myself if SPIFI is configured unproperly
   */
! #define ENABLE_SPIFI_RETRY  1
  
  /*
   *
***************
*** 101,106 ****
--- 101,123 ----
  		spifi_set_clock(/*try_18MHz=*/ 1);
  		spifi_initial_flash();
  	}
+ 
+ 	/*
+ 	 * try more high SCK
+ 	 *   288/ 8 => 36.0MHz => 0x0900_081c ...tested, no error (write/read)
+ 	 *   288/ 7 => 41.1MHz => 0x0900_0818
+ 	 *   288/ 6 => 48.0MHz => 0x0900_0814
+ 	 *   288/ 5 => 57.6MHz => 0x0900_0810
+ 	 *   288/ 4 => 72.0MHz => 0x0900_080c
+ 	 *   288/ 3 => 96.0MHz => 0x0900_0808
+ 	 * do this after initialization, because
+ 	 * lower speed needed in initial process
+ 	 *  | You can't increase the clock speed first because the driver
+ 	 *  | relies on being able to perform a JEDEC ID read which is
+ 	 *  | only supported on this Spansion part up to 50 MHz.
+ 	 */
+ 	IDIVB_CTRL = 0x09000810;	/* 58MHz */
+ //	IDIVB_CTRL = 0x0900080c;	/* 72MHz */
  
  	rprintf("select test\r\n");