/*
 * examine SPIFI-flash
 *   by uratan! 2012.11.11
 *   revised 2012.12.12
 */

basic behaviors (11 Nov 2012)

CONDITIONS

• tested by LPC1830-Xplorer. (chip revision A) (S25FL032P)
• the program is run on 0x1000_0000, by uart3-boot.
  (see main.c for action detail, other files are in test-spifi/* of minimon-011.zip)
• the core runs at 96MHz, and SPIFI interface clock is 18MHz.

001: continuous byte read ('1')

• 8bit * 8bytes / 16SCK = 4bit/SCK, quad mode may be effective.
• command and address may be sent by first 12SCKs.
• continuous command/address may be omitted by sequential access.
• it takes about 5 or 6 SCKs to data fed is ready. (including delay to GPIO)

002: repeat "continuous byte read" ('1')

• there is no access when repeated, some cache may be.
    ( 56nsec / 96MHz = 5.3clks ... almost no loss )

003,004: separated byte read ('2', '3')

• command/address may be sent everytime when non-continuous.
• read request for SPIFI may be always done by 8byte boundary.

005,006: byte in continuous boundary read ('4', '5')

• access for SPIFI is continuos when it is the best case, but will this occur when instruction read ?

simple instruction fetch (11 Nov 2012)

101,102: execute nops() from RAM / SPIFI ('n')

• instruction fetch can be done like best case, except branchs.
• running code from SPIFI-flash is 14 times slower than from RAM.
    1.5usec / 96MHz = 144clks
          ( (128+8)NOPs * 16bit/instruction / 16bit/clk = 136clks )
    20.8usec / 32MHz = 666SCKs
          ( (128+8)NOPs * 16bit/instruction / 4bit/SCK = 544SCKs )

103,104: execute nops() from SPIFI which is configured unproperly by boot-ROM ('n')

• running code from unproperly configured SPIFI-flash is 7 times slower than normal. SCK is decreased to 18MHz, data width may be 1bit.

tune params (22 Nov 2012)

CONDITIONS

• same as basic behaviors with patch1122.txt

201: separated byte read ('2', with changing CS_HIGH from 3 to 1)

• SPIFI command interval is shortened, about
    (1.82usec - 1.72usec) / 18MHz = 1.8SCKs
  
• ( test #1, #4, #5 may not be affected by this param, maybe because only single read is continued. )

202: separated byte read ('2', with changing SCK from 18MHz to 72MHz)

• 72MHz / 18MHz = 4
  1.72usec / 460nsec = 3.7
• ( plz ignore cross-talks, the bandwidth of my oscilloscope/probe is 100MHz... )

203,204: execute nops() from SPIFI ('n', SCK=58MHz)

• 58MHz / 32MHz = 1.8
  20.8usec / 12.5usec = 1.7
• ( I can not run at 72MHz on current settings / environments )
  ( sometimes the data can not be read correctly )

299: FYI: execute nops() on LPC2141 (from internal flash)

• 6.6usec / 24MHz = 158clks
    ( GPIO3_NOT = G3_5_MONI;   ==>   FIO0PIN ^= TP0_18; )

delay for interrput (28 Nov 2012)

CONDITIONS

• generate an interrupt by SW2 thru GPIO
• vector[] and handler() is always on RAM
  (see 2main.c for action detail, other files are in test-spifi2/* of minimon-012.zip)

301: interrupt while executing brchs() from RAM ('b')

• the timings are very stable. see 10 trace animation

302,303,304: interrupt while executing brchs() from SPIFI ('b')

• see 10 trace animation

305: simply execute brchs() from SPIFI ('b', phase monitor output is enabled)

• the traces are repeated, very stable. the 'rest' may be inserted by some logical reason...
• the delay of SPECIAL WORST SAMPLE case may be caused by this rest.
• 35usec / 32MHz = 1120SCK
  1120SCK / 34branch-instruction = 33 [SCKs/instruction]
  

  high-quality push-SW is added for the interrupt test.

epilogue (7 Dec 2012)

Above tests was done under the conditions of SPIFI interface below.   (FYI: patch1204.txt)

when uart3-boot --> [1]   (used for waveform 001-006, 101, 201,202, 301)
when SPIFI-boot --> [2]   (used for waveform 102, 203,204, 302-305)

SPIFI_CONTROL (0x4000_3000 [RW]) [1] +---------------------+---------------------+ 0x6803_FFFF | 0110 1000 0000 0011 | 1111 1111 1111 1111 | <==set by library call [2] +---------------------+---------------------+ 0x4009_FFFF | 0100 0000 0000 1001 | 1111 1111 1111 1111 | <==set at boot time +---------------------+---------------------+ || | | |||| || | | CS_HIGH || | MODE3 || DisablePreFETCH (thanks noahk) |FULLCLK RCVCLK (other bits are unknown yet)

If you will trace above tests, try it with changing params in the SPIFI_CONTROL register, especially CS_HIGH and DisablePreFETCH.
And compare misc process speed with/without inserting NOPs.

  - * - * -

If you want to use boot-ROM call for spifi_init() instead of it in the library, it may be better to SWAP 3rd and 4th params, like:

result = spifi_init_in_bootROM(obj, csHigh, CLOCK, options);

  (when chip revision A, boot-ROM version 11.1 @ 0x1040_7ffc)
    (see also the first comment in spifi.c)
      (you shall repeat this ROM call until success (only once or twice, maybe))
        (try also to pass 0 as CLOCK)

L

- * - * -

[12 Dec 2012]

Try also new 'spifi_drv_M3.lib' in the CMSIS package "lpc18xx-2012-12-11.zip".
I will, later, in the future...